Job Overview: This position is an excellent opportunity for an experienced and highly motivated verification engineer to join the growing System IP team!This is a fast-paced technical role employing the latest hardware design verification methodologies to develop complex and highly configurable hardware IP that sit at the heart of Arm-based Systems!
This role is for the Interconnect product team which develops the Arm Corelink Interconnect IP products.
Our Interconnects and NoCs are designed for intelligent connected systems across a wide range of applications including mobile, IoT, networking infrastructure, automotive etc.
The highly scalable IP is optimised for AMBA-compliant SoC connectivity and can be customised for multiple performance points.
Responsibilities: You will specify and develop new hardware verification testbenches for future generation hardware IP.
You will improve existing testbenches to increase performance, quality and efficiency.
You will also identify areas for improvement in methodologies and implement those changes to advance our best-practises for hardware verification.
Reviewing and assessing proposed design changes from a verification complexity point of view Ownership of verification environment from investigation all the way to verification closure Investigating and scripting new verification flows and optimising existing ones Analysis of data from simulation runs using machine learning and data science techniques to drive efficient bug discovery and coverage closure There will be opportunities for improving our verification methodology collaborating with arm engineering teams mentoring members of the team Required Skills and Experience : Can demonstrate experience in working with constrained-random verification including ownership of complex verification environment.
Experience of using SystemVerilog and UVM Proven software engineering skills including understanding of object-oriented programming, data structures, and algorithms.
You are competent developing verification flows, making the best use of EDA tools and have good scripting skills and are able to plan and estimate your own work.
'Nice To Have' Skills and Experience : Team leadership and mentoring experience Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e.g.
AMBA5 CHI, AMBA4 ACE or AXI) Experience in Formal Verification testbenches is a plus.
Strong communication and ability to work well as part of a team.
Dedicated with a focused approach to problem analysis and solving.
In return: You will get to utilise your engineering skills to develop technologies and influence millions of devices for years to come.
You will be able to drive and bring your ideas to a wider group of our leading experts, build your technical leadership and influencing skills towards becoming an established and recognised expert within the team.
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Hybrid Working at Arm Arm's approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing.
We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility.
Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team's needs.
Details of what this means for each role will be shared upon application.
In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution.
Please talk to us to find out more about what this could look like for you.
Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues.
We are a diverse organization of dedicated and innovative individuals, and don't discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.