Senior Engineer, Design Verification Engineering

Formal Verification Engineer - Cambridge (can do remote within the UK)
Is this the role you are looking for If so read on for more details, and make sure to apply today.
The successful candidate will be responsible for applying formal methods to verify the correctness of hardware designs, ensuring that the systems meet functional specifications and are free of design errors.
With projects already in full flow and partnerships with some global names, this is a great opportunity for Juniors and Seniors alike to join!
Use formal verification tools and techniques to verify digital designs at various levels of abstraction, including RTL and gate-level.
Identify design flaws, corner cases, and potential issues early in the design process using formal verification techniques.
Provide in-depth analysis and support for debugging and fixing issues.
Stay current with advancements in formal verification techniques, tools, and best practices.
Contribute to the development and adoption of new verification strategies to improve overall verification quality and efficiency.
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Hands-on experience with RTL design languages such as Verilog, SystemVerilog, or VHDL.
On offer is the chance to join an early stage start-up with a founder who has already had previous success within the Semiconductor space.
You will get equity and a competitive base salary.