Are you an experienced physical design engineer with a background in static timing analysis that is looking for a new role at a leading innovator in high-speed, energy-efficient chip-to-chip link solutions?
At European Tech Recruit we are working along side a highly innovative company, helping them to hire a senior physical design engineer in STA / timing to work on a hybrid remote basis in Northampton, UK.
Responsibilities: Developing and validating timing constraints, conducting sign-off Static Timing Analysis (STA), and supporting timing closure at both block and full-chip levels.
Performing STA for both block and chip levels, working with the design team to review and define constraints, implementing SDC constraints for STA, analyzing timing violations, and resolving them with the frontend design and physical design (PD) teams.
Contributing to the development of scripts, methodologies, and process improvements.
Collaborating closely with the design team to meet STA requirements and implement effective solutions.
Supporting IP and chip-level integration.
Requirements: Strong knowledge of RTL-to-GDS flow, including synthesis, place & route (P&R), logic equivalence checking (LEC), and STA.
Self-driven, with a strong sense of ownership and responsibility.
Excellent communication skills and a strong team player.
Proficient in scripting languages (shell, TCL, Python, make) and experienced in data management (revision control systems).
Experienced in gathering and defining SDC constraints, especially for top-level design, including DFT.
Requires excellent teamwork, perseverance, attention to detail, and the ability to collaborate effectively with team members to gather information.
Skilled in developing reusable workflows and processes across projects.
10+ years of experience in the semiconductor industry, with at least 5 years in a technical digital physical design role ( preferred ).
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