Formal Verification Engineer

Formal Verification Engineer Cambridge   I am seeking a Formal Verification Engineer to join an excellent Engineering team in their UK headquarters based in Cambridge.
As a Formal Verification Engineer, you will join a cutting-edge GPU team developing high-quality Formal Verification test benches to verify complex designs in GPU.
This position involves working with design and implementation teams to verify designs with high quality.
You must be proficient in debugging, deep bug hunting, formal tools, formal verification methodologies and processes to be considered.
Key Qualifications: Several years of ASIC design, verification, or related work experience.
Verification skills: Formal verification (Static and Dynamic), Assertion based verification.
System Verilog, Verilog or VHDL, Scripting skills required.
Design debug, Deep bug hunting, Formal test planning, Formal tools – Jasper, VC-formal.
Simulation based verification using UVM/System Verilog   As a top company, you can expect Salary, stock and performance related bonus, stock purchase scheme and an array of different insurances.
For more information, please contact Rachel Mason at IC Resources.