Dv Engineer

Job Title: DV Engineer [ASICS Engineering - Engineer] Remote 6 month contract (Contract until end of feb high possibility of it getting extended) Experience in UVM , Soc Methodology, Experience in developing test plans, test benches, AMBA Protocol, Debugging exp, exp with c model and language Formal Verification - Nyc to have Candidate requirements : • Experience in design and verification on SoCs and SoC Methodologies for verifying complex units on SoC using industry standard tools and technologies.
• Proficient in developing unit and subsystem level test benches using SV/UVM methodology.
• •Constrained random and Metrics driven verification.
• Experienced with C model integration and scorebording • FW code integration verification • Experience with AMBA protocols and BUS interconnect functional and formal verification along with coverage closure.
• Experience with power aware verification and clock domain crossing verification.
• Experience with debugging test failures • Strong knowledge of verification planning, coverage analysis, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog • Experience with Verilog, C/C++, System C, TCL/Perl/shell-scripting • Strong analytical skills and ability to work in a dynamic and fast paced team environment.
• Excellent communication skills 8-12 years of experience